![]() If you get your boards made professionally, you will be generating I'm curious though why they even have the option for the check? is there some problem using the proportional font on the copper layer? I'm planning on having the boards produced professionally, and I want to make sure they come out correctly. I found an option in the DRC under MISC for Font, if I take the checkmark out of it, I no longer get errors for using the proportional font on my bottom copper layer. The custom layer method I briefly mentioned before). Just "approve" all the errors or tackle the problem another way (such as It's probably better (certainly easier) either to It's possible to fix all the errors by laboriously tweaking each line to ![]() You will get airwires between the various lines. Note that crossing each other does not count as joining. If you name them all the same, Eagle willĪsk which name to merge the nets as but then it will expect the lines toĪll be joined. I don't think you can rename a group but you can rename individual I like the lettering of the proportional font better, is there a way to get it to accept this or can the error just be ignored / approved? But now I notice if I use the proportional font, I get an error for No Vector Font if it's on the bottom copper layer. ![]() I was able to get rid of the width error by fattening up the text a little. any thoughts on how to change or merge or connect the segments so they are part of the same net? Is there a way to force all the signal names of a group to a specific value? I thought I could perhaps group all connected segments together and use the change feature to change all the signal names, but I don't see a way to change that particular field. I suspect it has to do with the order the entities are saved in the DXF file, as it's only a few sections of my import that have this issue. Yes, this seems to be the case, some sections of the imported DXF file have different signal names. I have got almost everything working now except for the issue with DXF Import: Then arranging for that layer to be present in the Gerber (or printout, To do what you want by creating a new custom layer for all this stuff, That depends how you plan to produce the board. Now group the copies,ĭo CHANGE LAYER to put them on tMask/bMask, then MOVE the group back to What you do is group them all, "CUT" (the scissors icon, whichĪctually copies) then PASTE somewhere off-board. You can copy the text/graphics into the mask layer but it's not a single There's no overlap checking on the silk layer because the silk layer ![]() Is there a way to define these as graphics in copper or something so the DRC ignores it? Is there some way to combine the separate lines and arcs that got imported from the DXF file into a continuous trace so they don't show up as overlaps? When I import the same DXF file to the silk screen layer, it doesn't get any DRC errors. Gets its own net, so where they overlap it's an error. The DXF import probably creates a lot of separate lines, each of which I have managed to force traces by importing a DXF file to the bottom layer, but when I run DRC I get a whole list of overlap and clearance issues with the imported copper traces, The DRC error is because the text, when rendered, results in traces ofĬopper that are narrower than your DRC rules allow. Net name created for the segments, which isn't usually a problem. Not "traces" but you can draw on the copper layers with the "wire" Should I be putting things I just want to leave in copper on the bottom on some other layer besides bottom that will do what I want it to? Is there a way to automatically make holes in the solder mask only around the graphics traces, or text so the graphics or text end up coated with solder? I have managed to force traces by importing a DXF file to the bottom layer, but when I run DRC I get a whole list of overlap and clearance issues with the imported copper traces, is there a way to define these as graphics in copper or something so the DRC ignores it? Is there some way to combine the separate lines and arcs that got imported from the DXF file into a continuous trace so they don't show up as overlaps? When I import the same DXF file to the silk screen layer, it doesn't get any DRC errors. it even automatically makes it backwards when I select the bottom layer, but I still get the DRC error. I can add Text and define it to be on the bottom layer so it would be in copper, but I get an error in DRC for 'Width' which I don't understand because the lettering looks good to me. Is there any way to draw traces without pads? I have always left copper on the bottom side of the board for uses other than traces in empty areas of my circuit boards, things like company name, board numbers, terminal block pin designations, logos, etc, I have some questions about how to properly define such entitles in eagle so I do not get errors, and so the board will come out as I intend:
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